Scalable and Near-Optimal Design Space Exploration for Embedded Systems
Autor Principal: | |
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Otros autores o Colaboradores: | , |
Formato: | Libro |
Lengua: | inglés |
Datos de publicación: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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Temas: | |
Acceso en línea: | http://dx.doi.org/10.1007/978-3-319-04942-7 |
Resumen: | This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.  â_¢Â Describes design space exploration (DSE) methodologies for data storage and processing in embedded systems, which achieve near-optimal solutions with scalable exploration time; â_¢Â Presents a set of principles and the processes which support the development of the proposed scalable and near-optimal methodologies; â_¢Â Enables readers to apply scalable and near-optimal methodologies to the intra-signal in-place optimization step for both regular and irregular memory accesses. |
Descripción Física: | xvii, 277 p. : il. |
ISBN: | 9783319049427 |
DOI: | 10.1007/978-3-319-04942-7 |
Tabla de Contenidos:
- Introduction & Motivation
- Reusable DSE methodology for scalable & near-optimal frameworks
- Part I Background memory management methodologies
- Development of intra-signal in-place methodology
- Pattern representation
- Intra-signal in-place methodology for non-overlapping scenario
- Intra-signal in-place methodology for overlapping scenario
- Part II Processing related mapping methodologies
- Design-time scheduling techniques DSE framework
- Methodology to develop design-time scheduling techniques under constraints
- Design Exploration Methodology for Microprocessor & HW accelerators
- Conclusions & Future Directions.