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cr nn 008mamaa |
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140321s2014 gw | s |||| 0|eng d |
| 020 |
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|a 9783319049427
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| 024 |
7 |
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|a 10.1007/978-3-319-04942-7
|2 doi
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|a TK7888.4
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|a TJFC
|2 bicssc
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|a TEC008010
|2 bisacsh
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| 100 |
1 |
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|a Kritikakou, Angeliki.
|9 261051
|
| 245 |
1 |
0 |
|a Scalable and Near-Optimal Design Space Exploration for Embedded Systems
|h [libro electrónico] /
|c by Angeliki Kritikakou, Francky Catthoor, Costas Goutis.
|
| 260 |
|
1 |
|a Cham :
|b Springer International Publishing :
|b Imprint: Springer,
|c 2014.
|
| 300 |
|
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|a xvii, 277 p. :
|b il.
|
| 336 |
|
|
|a text
|b txt
|2 rdacontent
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| 337 |
|
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|a computer
|b c
|2 rdamedia
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| 338 |
|
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|a online resource
|b cr
|2 rdacarrier
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| 347 |
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|a text file
|b PDF
|2 rda
|
| 505 |
0 |
|
|a Introduction & Motivation -- Reusable DSE methodology for scalable & near-optimal frameworks -- Part I Background memory management methodologies -- Development of intra-signal in-place methodology -- Pattern representation -- Intra-signal in-place methodology for non-overlapping scenario -- Intra-signal in-place methodology for overlapping scenario -- Part II Processing related mapping methodologies -- Design-time scheduling techniques DSE framework -- Methodology to develop design-time scheduling techniques under constraints -- Design Exploration Methodology for Microprocessor & HW accelerators -- Conclusions & Future Directions.
|
| 520 |
|
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|a This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.  â_¢Â Describes design space exploration (DSE) methodologies for data storage and processing in embedded systems, which achieve near-optimal solutions with scalable exploration time; â_¢Â Presents a set of principles and the processes which support the development of the proposed scalable and near-optimal methodologies; â_¢Â Enables readers to apply scalable and near-optimal methodologies to the intra-signal in-place optimization step for both regular and irregular memory accesses.
|
| 650 |
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0 |
|a Engineering.
|9 259622
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| 650 |
|
0 |
|a Energy.
|9 259726
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| 650 |
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0 |
|a Microprocessors.
|9 259640
|
| 650 |
|
0 |
|a Electronics.
|9 259648
|
| 650 |
|
0 |
|a Microelectronics.
|9 259649
|
| 650 |
|
0 |
|a Electronic circuits.
|9 259798
|
| 650 |
2 |
4 |
|a Circuits and Systems.
|9 259651
|
| 650 |
2 |
4 |
|a Processor Architectures.
|9 259645
|
| 650 |
2 |
4 |
|a Instrumentation.
|9 259652
|
| 700 |
1 |
|
|a Catthoor, Francky.
|9 261052
|
| 700 |
1 |
|
|a Goutis, Costas.
|9 261053
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783319049410
|
| 856 |
4 |
0 |
|u http://dx.doi.org/10.1007/978-3-319-04942-7
|
| 912 |
|
|
|a ZDB-2-ENG
|
| 929 |
|
|
|a COM
|
| 942 |
|
|
|c EBK
|6 _
|
| 950 |
|
|
|a Engineering (Springer-11647)
|
| 999 |
|
|
|a SKV
|c 27862
|d 27862
|
