High-Bandwidth Memory Interface

Detalles Bibliográficos
Autor Principal: Kim, Chulwoo
Otros autores o Colaboradores: Lee, Hyun-Woo, Song, Junyoung
Formato: Libro
Lengua:inglés
Datos de publicación: Cham : Springer International Publishing : Imprint: Springer, 2014.
Series:SpringerBriefs in Electrical and Computer Engineering,
Temas:
Acceso en línea:http://dx.doi.org/10.1007/978-3-319-02381-6
Resumen:This book provides an overview of recent advances in memory interface design at both the architecture and circuit levels. Coverage includes signal integrity and testing, TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation, and clock generation and distribution. Trends for further bandwidth enhancement are also covered.   â_¢Â Enables readers with minimal background in memory design to understand the basics of high-bandwidth memory interface design; â_¢Â Presents state-of-the-art techniques for memory interface design; â_¢Â Covers memory interface design at both the circuit level and system architecture level.
Descripción Física:viii, 88 p. : il.
ISBN:9783319023816
ISSN:2191-8112
DOI:10.1007/978-3-319-02381-6

MARC

LEADER 00000Cam#a22000005i#4500
001 INGC-EBK-000283
003 AR-LpUFI
005 20220927105748.0
007 cr nn 008mamaa
008 131027s2014 gw | s |||| 0|eng d
020 |a 9783319023816 
024 7 |a 10.1007/978-3-319-02381-6  |2 doi 
050 4 |a TK7888.4 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
100 1 |a Kim, Chulwoo.  |9 260661 
245 1 0 |a High-Bandwidth Memory Interface   |h [libro electrónico] /   |c by Chulwoo Kim, Hyun-Woo Lee, Junyoung Song. 
260 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2014. 
300 |a viii, 88 p. :   |b il. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
490 1 |a SpringerBriefs in Electrical and Computer Engineering,  |x 2191-8112 
505 0 |a An introduction to high-speed DRAM -- An I/O Line Configuration and Organization of DRAM -- Clock generation and distribution -- Transceiver Design -- TSV Interface for DRAM. 
520 |a This book provides an overview of recent advances in memory interface design at both the architecture and circuit levels. Coverage includes signal integrity and testing, TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation, and clock generation and distribution. Trends for further bandwidth enhancement are also covered.   â_¢Â Enables readers with minimal background in memory design to understand the basics of high-bandwidth memory interface design; â_¢Â Presents state-of-the-art techniques for memory interface design; â_¢Â Covers memory interface design at both the circuit level and system architecture level. 
650 0 |a Engineering.  |9 259622 
650 0 |a Electronic circuits.  |9 259798 
650 0 |a Electronics.  |9 259648 
650 0 |a Microelectronics.  |9 259649 
650 2 4 |a Circuits and Systems.  |9 259651 
650 2 4 |a Electronic Circuits and Devices.  |9 260105 
650 2 4 |a Instrumentation.  |9 259652 
700 1 |a Lee, Hyun-Woo.  |9 260662 
700 1 |a Song, Junyoung.  |9 260663 
776 0 8 |i Printed edition:  |z 9783319023809 
856 4 0 |u http://dx.doi.org/10.1007/978-3-319-02381-6 
912 |a ZDB-2-ENG 
929 |a COM 
942 |c EBK  |6 _ 
950 |a Engineering (Springer-11647) 
999 |a SKV  |c 27711  |d 27711