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cr nn 008mamaa |
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131115s2014 gw | s |||| 0|eng d |
| 020 |
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|a 9783319023786
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| 024 |
7 |
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|a 10.1007/978-3-319-02378-6
|2 doi
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|a TK7888.4
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|a TJFC
|2 bicssc
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| 072 |
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|a TEC008010
|2 bisacsh
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| 100 |
1 |
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|a Noia, Brandon.
|9 260659
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| 245 |
1 |
0 |
|a Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
|h [libro electrónico] /
|c by Brandon Noia, Krishnendu Chakrabarty.
|
| 260 |
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1 |
|a Cham :
|b Springer International Publishing :
|b Imprint: Springer,
|c 2014.
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| 300 |
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|a xviii, 245 p. :
|b il.
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 347 |
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|a text file
|b PDF
|2 rda
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| 505 |
0 |
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|a Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.
|
| 520 |
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|a This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.  â_¢Â Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; â_¢Â Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; â_¢Â Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  .
|
| 650 |
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0 |
|a Engineering.
|9 259622
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| 650 |
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0 |
|a Microprocessors.
|9 259640
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| 650 |
|
0 |
|a Semiconductors.
|9 259967
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| 650 |
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0 |
|a Electronic circuits.
|9 259798
|
| 650 |
2 |
4 |
|a Circuits and Systems.
|9 259651
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| 650 |
2 |
4 |
|a Processor Architectures.
|9 259645
|
| 700 |
1 |
|
|a Chakrabarty, Krishnendu.
|9 260660
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783319023779
|
| 856 |
4 |
0 |
|u http://dx.doi.org/10.1007/978-3-319-02378-6
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| 912 |
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|a ZDB-2-ENG
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| 929 |
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|a COM
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| 942 |
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|c EBK
|6 _
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| 950 |
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|a Engineering (Springer-11647)
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| 999 |
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|a SKV
|c 27710
|d 27710
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