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20220927105705.0 |
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cr nn 008mamaa |
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130918s2014 gw | s |||| 0|eng d |
| 020 |
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|a 9783319006819
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| 024 |
7 |
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|a 10.1007/978-3-319-00681-9
|2 doi
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| 050 |
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4 |
|a TK7888.4
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| 072 |
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7 |
|a TJFC
|2 bicssc
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| 072 |
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7 |
|a TEC008010
|2 bisacsh
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| 100 |
1 |
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|a Sun, Guangyu.
|9 260352
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| 245 |
1 |
0 |
|a Exploring Memory Hierarchy Design with Emerging Memory Technologies
|h [libro electrónico] /
|c by Guangyu Sun.
|
| 260 |
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1 |
|a Cham :
|b Springer International Publishing :
|b Imprint: Springer,
|c 2014.
|
| 300 |
|
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|a vii, 122 p. :
|b il.
|
| 336 |
|
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|a text
|b txt
|2 rdacontent
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| 337 |
|
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|a computer
|b c
|2 rdamedia
|
| 338 |
|
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|a online resource
|b cr
|2 rdacarrier
|
| 347 |
|
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|a text file
|b PDF
|2 rda
|
| 490 |
1 |
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|a Lecture Notes in Electrical Engineering,
|x 1876-1100 ;
|v 267
|
| 505 |
0 |
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|a Introduction -- Replacing Different Levels of the Memory Hierarchy with NVMs -- Moguls: a Model to Explore the Memory Hierarchy for Throughput Computing -- Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory.
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| 520 |
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|a This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the â_omemory wall.â__ The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification;  hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named â_oMogulsâ__ is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.  ·        Provides a holistic study of using emerging memory technologies in different levels of the memory hierarchy; ·        Equips readers with techniques for memory design with improved performance, energy consumption, and reliability; ·        Includes coverage of all memory levels, ranging from cache to storage; ·        Explains how to choose the proper memory technologies in different levels of the memory hierarchy.
|
| 650 |
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0 |
|a Engineering.
|9 259622
|
| 650 |
|
0 |
|a Microprocessors.
|9 259640
|
| 650 |
|
0 |
|a Semiconductors.
|9 259967
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| 650 |
|
0 |
|a Electronic circuits.
|9 259798
|
| 650 |
2 |
4 |
|a Circuits and Systems.
|9 259651
|
| 650 |
2 |
4 |
|a Processor Architectures.
|9 259645
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9783319006802
|
| 856 |
4 |
0 |
|u http://dx.doi.org/10.1007/978-3-319-00681-9
|
| 912 |
|
|
|a ZDB-2-ENG
|
| 929 |
|
|
|a COM
|
| 942 |
|
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|c EBK
|6 _
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| 950 |
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|a Engineering (Springer-11647)
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| 999 |
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|a SKV
|c 27605
|d 27605
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