Routing Algorithms in Networks-on-Chip

Detalles Bibliográficos
Otros autores o Colaboradores: Palesi, Maurizio (ed.), Daneshtalab, Masoud (ed.)
Formato: Libro
Lengua:inglés
Datos de publicación: New York, NY : Springer New York : Imprint: Springer, 2014.
Temas:
Acceso en línea:http://dx.doi.org/10.1007/978-1-4614-8274-1
Resumen:This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation; ·         Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance.
Descripción Física:xiv, 410 p. : il.
ISBN:9781461482741
DOI:10.1007/978-1-4614-8274-1

MARC

LEADER 00000Cam#a22000005i#4500
001 INGC-EBK-000105
003 AR-LpUFI
005 20220927105633.0
007 cr nn 008mamaa
008 131022s2014 xxu| s |||| 0|eng d
020 |a 9781461482741 
024 7 |a 10.1007/978-1-4614-8274-1  |2 doi 
050 4 |a TK7888.4 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
245 1 0 |a Routing Algorithms in Networks-on-Chip   |h [libro electrónico] /   |c edited by Maurizio Palesi, Masoud Daneshtalab. 
260 1 |a New York, NY :  |b Springer New York :  |b Imprint: Springer,  |c 2014. 
300 |a xiv, 410 p. :   |b il. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Part I Performance Improvement -- Basic Concepts on On-Chip Networks -- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs -- Run-Time Deadlock Detection -- The Abacus Turn Model -- Learning-based Routing Algorithms for on-Chip Networks -- Part II Multicast Communication -- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip -- Path-based Multicast Routing for 2D and 3D Mesh Networks -- Part III Fault Tolerance and Reliability -- Fault-Tolerant Routing Algorithms in Networks-on-Chip -- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip. 
520 |a This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation; ·         Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance. 
650 0 |a Engineering.  |9 259622 
650 0 |a Microprocessors.  |9 259640 
650 0 |a Electronics.  |9 259648 
650 0 |a Microelectronics.  |9 259649 
650 0 |a Electronic circuits.  |9 259798 
650 2 4 |a Circuits and Systems.  |9 259651 
650 2 4 |a Processor Architectures.  |9 259645 
650 2 4 |a  Instrumentation.  |9 259652 
700 1 |a Palesi, Maurizio,   |e ed.  |9 260113 
700 1 |a Daneshtalab, Masoud,   |e ed.  |9 260114 
776 0 8 |i Printed edition:  |z 9781461482734 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4614-8274-1 
912 |a ZDB-2-ENG 
929 |a COM 
942 |c EBK  |6 _ 
950 |a Engineering (Springer-11647) 
999 |a SKV  |c 27533  |d 27533